Architecture and interconnect scheme for programmable logic circuits

ABSTRACT

An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part (CIP) application ofSer. No. 08/101,197; filed Aug. 3, 1993, which is assigned to theassignee of the present invention.

FIELD OF THE INVENTION

[0002] The present invention pertains to the field of programmable logiccircuits. More particularly, the present invention relates to anarchitecture and interconnect scheme for programmable logic circuits.

BACKGROUND OF THE INVENTION

[0003] When integrated circuits (ICs) were first introduced, they wereextremely expensive and were limited in their functionality. Rapidstrides in semiconductor technology have vastly reduced the cost whilesimultaneously increased the performance of IC chips. However, thedesign, layout, and fabrication process for a dedicated, custom built ICremains quite costly. This is especially true for those instances whereonly a small quantity of a custom designed IC is to be manufactured.Moreover, the turn-around time (i.e., the time from initial design to afinished product) can frequently be quite lengthy, especially forcomplex circuit designs. For electronic and computer products, it iscritical to be the first to market. Furthermore, for custom ICs, it israther difficult to effect changes to the initial design. It takes time,effort, and money to make any necessary changes.

[0004] In view of the shortcomings associated with custom IC's, fieldprogrammable gate arrays (FPGAs) offer an attractive solution in manyinstances. Basically, FPGAs are standard, high-density, off-the-shelfICs which can be programmed by the user to a desired configuration.Circuit designers first define the desired logic functions, and the FPGAis programmed to process the input signals accordingly. Thereby, FPGAimplementations can be designed, verified, and revised in a quick andefficient manner. Depending on the logic density requirements andproduction volumes, FPGAs are superior alternatives in terms of cost andtime-to-market.

[0005] A typical FPGA essentially consists of an outer ring of I/Oblocks surrounding an interior matrix of configurable logic blocks. TheI/O blocks residing on the periphery of an FPGA are user programmable,such that each block can be programmed independently to be an input oran output and can also be tri-statable. Each logic block typicallycontains programmable combinatorial logic and storage registers. Thecombinatorial logic is used to perform boolean functions on its inputvariables. Often, the registers are loaded directly from a logic blockinput, or they can be loaded from the combinatorial logic.

[0006] Interconnect resources occupy the channels between the rows andcolumns of the matrix of logic blocks and also between the logic blocksand the I/O blocks. These interconnect resources provide the flexibilityto control the interconnection between two designated points on thechip. Usually, a metal network of lines run horizontally and verticallyin the rows and columns between the logic blocks. Programmable switchesconnect the inputs and outputs of the logic blocks and I/O blocks tothese metal lines. Crosspoint switches and interchanges at theintersections of rows and columns are used to switch signals from oneline to another. Often, long lines are used to run the entire lengthand/or breadth of the chip.

[0007] The functions of the I/O blocks, logic blocks, and theirrespective interconnections are all programmable. Typically, thesefunctions are controlled by a configuration program stored in an on-chipmemory. The configuration program is loaded automatically from anexternal memory upon power-up, on command, or programmed by amicroprocessor as part of system initialization.

[0008] The concept of FPGA was summarized in the sixty's by Minnick whodescribed the concept of cell and cellular array as reconfigurabledevices in the following documents: Minnick, R. C. and Short, R. A.,“Cellular Linear-Input Logic, Final Report,” SRI Project 4122, ContractAF 19(628)-498, Stanford Research Institute, Menlo Park, Calif., AFCRL64-6, DDC No. AD 433802(February 1964); Minnick, R. C., “Cobweb CellularArrays,” Proceedings AFIPS 1965 Fall Joint Computer Conference, Vol. 27,Part 1 pp. 327-341 (1965); Minnick, R. C. et al., “Cellular Logic, FinalReport,” SRI Project 5087, Contract AF 19(628)-4233, Stanford ResearchInstitute, Menlo Park, Calif., AFCRL 66-613, (April 1966); and Minnick,R. C., “A Survey of Microcellular Research,” Journal of the Associationfor Computing Machinery, Vol. 14, No. 2, pp. 203-241 (April 1967). Inaddition to memory based (e.g., RAM-based, fuse-based, orantifuse-based) means of enabling interconnects between devices, Minnickalso discussed both direct connections between neighboring cells and useof busing as another routing technique. The article by Spandorfer, L.M., “Synthesis of Logic Function on an Array of Integrated Circuits,”Stanford Research Institute, Menlo Park, Calif., Contract AF19(628)2907, AFCRL 64-6, DDC No. AD 433802 (November 1965), discussedthe use of complementary MOS bi-directional passgate as a means ofswitching between two interconnect lines that can be programmed throughmemory means and adjacent neighboring cell interconnections. InWahlstrom, S. E., “Programmable Logic Arrays—Cheaper by the Millions,”Electronics, Vol. 40, No. 25, 11, pp. 90-95 (December 1967), aRAM-based, reconfigurable logic array of a two-dimensional array ofidentical cells with both direct connections between adjacent cells anda network of data buses is described.

[0009] Shoup, R. G., “Programmable Cellular Logic Arrays,” Ph.D.dissertation, Carnegie-Mellon University, Pittsburgh, Pa. (March 1970),discussed programmable cellular logic arrays and reiterates many of thesame concepts and terminology of Minnick and recapitulates the array ofWahlstrom. In Shoup's thesis, the concept of neighbor connectionsextends from the simple 2-input 1-output nearest-neighbor connections tothe 8-neighbor 2-way connections. Shoup further described use of bus aspart of the interconnection structure to improve the power andflexibility of an array. Buses can be used to route signals overdistances too long, or in inconvenient directions, for ordinary neighborconnections. This is particularly useful in passing inputs and outputsfrom outside the array to interior cells.

[0010] U.S. Pat. No. 4,020,469 discussed a programmable logic array thatcan program, test, and repair itself. U.S. Pat. No. 4,870,302 introduceda coarse grain architecture without use of neighbor directinterconnections where all the programmed connections are through theuse of three different sets of buses in a channeled architecture. Thecoarse grain cell (called a Configurable Logical block or CLB) containsboth RAM-based logic table look up combinational logic and flip flopsinside the CLB where a user defined logic must be mapped into thefunctions available inside the CLB. U.S. Pat. No. 4,935,734 introduced asimple logic function cell defined as a NAND, NOR or similar types ofsimple logic function inside each cell. The interconnection scheme isthrough direct neighbor and directional bus connections. U.S. Pat. Nos.4,700,187 and 4,918,440defined a more complex logic function cell wherean Exclusive OR and AND functions and a register bit is available andselectable within the cell. The preferred connection scheme is throughdirect neighbor connections. Use of bi-direction buses as connectionswere also included.

[0011] Current FPGA technology has a few shortcomings. These problemsare embodied by the low level of circuit utilization given the vastnumber of transistors available on chip provided by the manufacturers.Circuit utilization is influenced by three factors. The first one at thetransistor or fine grain cell level is the function and flexibility ofthe basic logic element that can be readily used by the users. Thesecond one is the ease in which to form meaningful macro logic functionsusing the first logic elements with minimum waste of circuit area. Thelast factor is the interconnections of those macro logic functions toimplement chip level design efficiently. The fine grained cellarchitectures such as those described above, provided easily usable andflexible logical functions for designers at the base logic elementlevel.

[0012] However, for dense and complex macro functions and chip levelrouting, the interconnection resources required to connect a largenumber of signals from output of a cell to the input(s) of other cellscan be quickly exhausted, and adding these resources can be veryexpensive in terms of silicon area. As a consequence, in fine grainedarchitecture design, most of the cells are either left unused due toinaccessibility, or the cells are used as interconnect wires instead oflogic. This adds greatly to routing delays in addition to low logicutilization, or excessive amount of routing resources are added, greatlyincreasing the circuit size. The coarse grain architecture coupled withextensive routing buses allows significant improvements for signalsconnecting outputs of a CLB to inputs of other CLBs. The utilization atthe CLB interconnect level is high. However, the difficulty is thepartitioning and mapping of complex logic functions so as to exactly fitinto the CLBs. If a part of logic inside the CLB is left unused, thenthe utilization (effective number of gates per unit area used) insidethe CLB can be low.

[0013] Another problem with prior art FPGAs is due to the fact thattypically a fixed number of inputs and a fixed number of outputs areprovided for each logic block. If, by happenstance, all the outputs of aparticular logic block is used up, then the rest of that logic blockbecomes useless.

[0014] Therefore, there is a need in prior art FPGAs for a newarchitecture that will maximize the utilization of an FPGA whileminimizing any impact on the die size. The new architecture shouldprovide flexibility in the lowest logic element level in terms offunctionality and flexibility of use by users, high density per unitarea functionality at the macro level where users can readily formcomplex logic functions with the base logic elements, and finally highpercentage of interconnectability with a hierarchical, uniformlydistributed routing network for signals connecting macros and base logicelements at the chip level. Furthermore, the new architecture shouldprovide users with the flexibility of having the number of inputs andoutputs for individual logical block be selectable and programmable, anda scalable architecture to accommodate a range of FPGA sizes.

SUMMARY OF THE INVENTION

[0015] The present invention relates to an architecture of logic andconnection scheme for programmable logic circuits, such as those forfield programmable gate arrays (FPGAs). The programmable logic circuitis comprised of a number of cells which perform digital functions oninput signals. Depending on user's specific design, certain cells areprogrammably interconnected to a particular configuration for realizingthe desired logic functions.

[0016] In the currently preferred embodiment, four logic cells (fourtwo-input one-output logic gates and one D flip-flop) form a logicalcluster (i.e. a 2×2 cell array) and four sets of clusters form a logicalblock (i.e. a 4×4 cell array). Within each cluster, there is a set offive intraconnection lines, called Intraconnection Matrix (I-Matrix),one associated with the output of each one of the four gates and the Dflip-flop that is connectable to the input of the other cells. Withineach logical block, the I-Matrix within each cluster can be extended toan adjacent cluster through a passgate to form connections within thelogical block (to extend the intraconnection range). Inside each logicalblock, there is an associated set of access lines called BlockConnectors (BCs). The block connectors provide access to andconnectability between the various cells of that same logical block. Inother words, each input and output of each of the cells of a logicalblock is capable of being connected to a set of block connectorscorresponding to that logical block. With the judicious use of I-Matrixand block connectors within the same logical block, a set of signals canbe internally connected without using any resources outside the logicalblock. A number of programmable switches are used to control which ofthe block connectors are to be connected together to a set of inputsand/or outputs of the cells inside the logical block for external accessconnecting to signals outside the current logical block. In other words,the input and/or output pins inside a logical block that are to beexternally connected outside of the current logical block are accessedor connected through block connectors within the current logical block.

[0017] In order to route signals between the various logical blocks, auniformly distributed multiple level architecture (MLA) routing networkis used to provide connectability between each of the individual sets ofblock connectors. Programmable switches are implemented to control whichof the first level MLA routing network lines are to be connectedtogether. Additional programmable switches are used to control which ofthe block connectors are to be connected to specific first level MLArouting lines. For example, the switches can be programmed to allow anoriginating cell belonging to one logical block to be connected to adestination cell belonging to a different logical block. This can beaccomplished by connecting the originating cell through one or more ofits block connectors, onto the first level MLA, depending on thedistance, other level(s) of MLA, and down through descending levels ofMLAs back to the first level MLA, and finally through the blockconnector of the destination cell. Thereby, the block connectors andfirst level of MLA routing network provide interconnectability for an8×8 cell array, called a block cluster.

[0018] In the present invention, larger cell arrays can beinterconnected by implementing additional levels of MLA routingnetworks. For example, connectability for a 16x16 cell array, called ablock sector, can be achieved by implementing a second level of MLArouting network lines to provide connectability between the variousfirst level of MLA routing lines thereby making connections betweendifferent block clusters. Each level of MLA has a corresponding numberof switches for providing programmable interconnections of the routingnetwork of that level. Additional switching exchange networks are usedto provide connectability between the various levels of MLAs.

[0019] In one embodiment, switches are used to provide connectabilitybetween two different sets of block connectors. Moreover, switches canbe included to provide connectability between different sets of MLArouting lines of a particular level of MLAs. This provides for increasedrouting flexibility.

[0020] In the present invention, all MLA routing network lines arebi-directional. The switches are comprised of programmablebi-directional passgates. For increased number of levels, drivers may benecessary for providing the necessary switching speed for driving therouting lines, passgates, and associated loads, etc. In one embodiment,switches are used to provide programmable connectability amongst varioussets of block connectors. Additional switches can be implemented toprovide programmable connectability amongst various sets of the firstlevel of MLA. This scheme can be repeated for higher levels of MLAs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is illustrated by way of example, and notby way of limitation, in the figures of the accompanying drawings and inwhich like reference numerals refer to similar elements and in which:

[0022]FIG. 1 is a block diagram of a field programmable gate array logicupon which the present invention may be practiced.

[0023]FIG. 2A shows one example of an individual cell.

[0024]FIG. 2B shows another example of an individual cell.

[0025]FIG. 3A shows a logical cluster.

[0026]FIG. 3B shows the extension of I-matrix intraconnections of alogical cluster to a neighboring logical cluster.

[0027]FIG. 4A shows an example of a logical cluster with vertical blockconnectors.

[0028]FIG. 4B shows an example of a logical cluster with horizontalblock connectors.

[0029]FIG. 5A shows the eight block connector to level 1 MLA exchangenetworks associated with a logical block and level 1 MLA turn points.

[0030]FIG. 5B shows a level 1 MLA turn point.

[0031]FIG. 5C shows an exchange network.

[0032]FIG. 6 shows the routing network for a block cluster.

[0033]FIG. 7A shows the block diagram of a block sector.

[0034]FIG. 7B shows a level 1 to level 2 MLA routing exchange network.

[0035]FIG. 8A shows a sector cluster.

[0036]FIG. 8B shows a level 2 to level 3 MLA routing exchange network.

[0037]FIG. 9 shows one embodiment of a hierarchical multiple levelrouting network for providing routability between the logical blocks andthe MLA levels.

[0038]FIG. 10 shows another embodiment of a hierarchical multiple levelrouting network for providing routability between the logical blocks andthe MLA levels.

[0039]FIG. 11 shows a block diagram of one embodiment of thehierarchical routing network wherein two groups of block connectorsaccess the same MLA lines.

[0040]FIG. 12 shows a block diagram of part of the multiple levelrouting network which encompasses Block Connectors to the MLA-3 Levelwith MLA Tabs for higher levels of routing network.

[0041]FIG. 13 shows an MLA-1 turn network.

[0042]FIG. 14 shows an MLA-2 turn network.

[0043]FIG. 15 shows an MLA-3 turn network.

[0044]FIG. 16 shows one embodiment of a routing network for the MLA-4layer and the mechanism whereby the MLA-4 lines are accessed.

[0045]FIG. 17 shows three different switch embodiments.

[0046]FIG. 18 shows one embodiment of a routing network for the MLA-5layer and the mechanism whereby MLA-5 lines are accessed.

DETAILED DESCRIPTION

[0047] An architecture and interconnect scheme for programmable logiccircuits is described. In the following description, for purposes ofexplanation, numerous specific details are set forth, such ascombinational logic, cell configuration, numbers of cells, etc., inorder to provide a thorough understanding of the present invention. Itwill be obvious, however, to one skilled in the art that the presentinvention may be practiced without these specific details. In otherinstances, well-known structures and devices are shown in block diagramform in order to avoid unnecessarily obscuring the present invention. Itshould also be noted that the present invention pertains to a variety ofprocesses including but not limited to static random access memory(SRAM), dynamic random access memory (DRAM), fuse, anti-fuse, erasableprogrammable read only memory (EPROM), electrically erasableprogrammable read only memory (EEPROM), FLASH, and ferroelectricprocesses.

[0048] Referring to FIG. 1, a block diagram of a field programmable gatearray logic upon which the present invention may be practiced is shownas 100. The I/O logical blocks 102, 103, 111 and 112 provide aninterface between external package pins of the FPGA and the internaluser logic either directly or through the I/O to Core interface 104,105, 113, and 114. Four interface blocks 104, 105, 113, and 114 providedecoupling between core 106 and the I/O logic 102, 103, 111, and 112.Core 106 is comprised of a number of clusters 107 which areintraconnected by I-Matrix 101 and interconnected by MLA routing network108.

[0049] Control/programming logic 109 is used to control all of the bitsfor programming the bit and word lines. For anti-fuse or fusetechnology, high voltage/current is applied to either zap or connect afuse. For EEPROM, Flash, or ferroelectric technology, there is an erasecycle followed by a programming cycle for programming the logic statesof the memory bits. In order to minimize skewing, a separate clock/resetlogic 110 is used to provide clock and reset lines on a group basis.

[0050] In the currently preferred embodiment, each of the clusters 107is comprised of a 2×2 hierarchy of four cells, called a logical cluster.FIGS. 2A and 2B show examples of individual cells 200 and 250. Cell 200performs multiple logic functions on two input signals (A and B) andprovides an output signal X. In the currently preferred embodiment, cell200 is comprised of an XOR gate 201, a two-input NAND gate 202, and atwo-input NOR gate 203. It should be noted, however, that in otherembodiments, cell 200 can include various other types and/orcombinations of gates. Cell 250 is comprised of cell 200 coupled with aD flip flop cell 260. The output X of cell 200 can be programmed toconnect directly to the data input D of the D flip flop gate 204 byactivating switch 218. The data input D can be accessed as a third inputof the combined cell 250.

[0051] Each of the two input signals A and B and the D input of Dflip-flop can be inverted or non-inverted, depending on the states ofswitches 206-211. Activating switches 206, 208 and 210 causes signals A,B and D to be driven by drivers 212-214 to gates 201-204 in anon-inverted fashion. Activating switches 207, 209, and 211 causes theinput signals A, B and D to be inverted by inverters 215-217 beforebeing passed to gates 201-204. The six switches 212-217 can individuallybe turned on and off as programmed by the user.

[0052] Note that the XOR gate 201, NAND gate 202, and NOR gate 203 canalso be used to perform XNOR, AND and OR by propagating the outputsignal to the next stage, whereby the signal can be inverted asdiscussed above.

[0053] Three switches 219-221 are respectively coupled to the outputs ofthe three gates 201-203. Again, these switches are programmable by theuser. Thereby, the user can specify which of the outputs from the gates201-203 is to be sent to driver 224 as the output X from cell 200.

[0054] The aforementioned switches 206-211, 218-221 are comprised ofbi-directional, program-controlled passgates. Depending on the state ofthe control signal, the switches are either conducting (i.e. passes asignal on the line) or non-conducting (i.e. does not pass the signal onthe line). Switches mentioned in the following sections are similarlycomprised of program-controlled passgates.

[0055] Referring now to FIG. 3A, a logical cluster 107 is shown. In thecurrently preferred embodiment, logical cluster 107 is comprised of fourcells 301-304 and a D flip-flop 305, twenty five switches 306-330, andfive intraconnection lines 331-335. The Intraconnection lines 331-335and switches 306-330 form the I-Matrix. I-Matrix provide connectabilityof the output, X, of each of the four cells 301-304, and the output X ofthe D flip-flop 305 to at least one input of each of the other threecells and the D flip-flop. For example, the output X of cell 301 can beconnected to input A of cell 302 by enabling switches 306 and 307.Likewise, the output X of cell 301 can be connected to input B of cell303 by enabling switches 306 and 310. Output X of cell 301 can beconnected to input A of cell 304 by enabling switches 306 and 308.Output X of cell 301 can be connected to input D of the D flip-flop cell305 by enabling switches 306 and 309.

[0056] Similarly, the output X from cell 302 can be connected to input Aof cell 301 by enabling switches 311 and 312. The output X from cell 302can be connected to input A of cell 303 by enabling switches 311 and315. The output X from cell 302 can be connected to input B of cell 304by enabling switches 311 and 313. Output X of cell 302 can be connectedto input D of the D flip-flop cell 305 by enabling switches 311 and 314.

[0057] Similarly, the output X from cell 303 can be connected to input Bof cell 301 by enabling switches 326 and 327. The output X from cell 303can be connected to input A of cell 302 by enabling switches 326 and328. The output X from cell 303 can be connected to input B of cell 304by enabling switches 326 and 329. Output X of cell 303 can be connectedto input D of the D flip-flop cell 305 by enabling switches 326 and 330.

[0058] For cell 304, the output X from cell 304 can be connected toinput B of cell 301 by enabling switches 316 and 317. The output X fromcell 304 can be connected to input B of cell 302 by enabling switches316 and 318. The output X from cell 304 can be connected to input A ofcell 303 by enabling switches 316 and 319. Output X of cell 304 can beprogrammably connected to input D of the D flip-flop cell 305 byenabling switch 218 in FIG. 2A.

[0059] With respect to cell 305, its output is connectable to the Ainput of cell 301 by enabling switches 320 and 321; the B input of cell302 by enabling switches 320 and 322; the B input of cell 303 byenabling switches 320 and 325; the A input of cell 304 by enablingswitches 320 and 323; and the D input of cell 305 itself by enablingswitches 320 and 324.

[0060] It can be seen that each output of the cells 301-304 and of the Dflip-flop 305 is connectable to the input of each of its neighboringcells and/or flip-flop inside the cluster.

[0061] In the currently preferred embodiment of the present invention,each logical cluster is connectable to all the other logical clustersinside each logical block through passgate switches extending theI-Matrix from neighboring clusters inside each logical block. FIG. 3Billustrates the extension of I-Matrix intraconnection lines 331-335 ofthe cells 301-304 and the D flip-flop 305 of a logical cluster 107 to aneighboring logical cluster 107 through the passgate switches 336-355within the same logical block.

[0062] In the currently preferred embodiment of the present invention,each logical block is connectable to all the other logical blocks of theFPGA. This is accomplished by implementing an architecture with multiplelayers of interconnections. It is important to note that this multiplelayers routing architecture is a conceptual hierarchy, not a process ortechnology hierarchy and is hence readily implementable with today'ssilicon process technology. The bottom most layer of interconnections isreferred to as the “block connectors”. A set of block connectorsprovides the access and interconnections of signals within an associatedlogical block (which is consisted of four logical clusters or 16 cells).Thereby, different sets of logical clusters within the same logicalblock are connectable to any of the other logical clusters within thatgroup through the use of extended I-Matrix and/or block connectors.Again, programmable bi-directional passgates are used as switches toprovide routing flexibility to the user.

[0063] The next level of connections is referred to as the “level 1Multiple Level Architecture (MLA)” routing network. The level 1 MLArouting network provides the interconnections between several sets ofblock connectors. Programmable passgates switches are used to provideusers with the capability of selecting which of the block connectors areto be connected. Consequently, a first logical block from one set oflogical block groups is connectable to a second logical block belongingto the same group. The appropriate switches are enabled to connect theblock connectors of the first logical block to the routing lines of thelevel 1 MLA routing network. The appropriate switches of the level 1 MLArouting network are enabled to provide the connections to the blockconnectors of the second logical block to the routing lines of the level1 MLA routing network. The appropriate switches are enabled to connectthe routing lines of the level 1 MLA routing network that connected tothe block connectors of the first and the second logical blocks.Furthermore, the user has the additional flexibility of programming thevarious switches within any given logical block to effect the desiredintraconnections between each of the cells of any logical block.

[0064] The next level of connections is referred to as the “level 2Multiple Level Architecture (MLA)” routing network. The level 2 MLAprovides the interconnections to the various level 1 MLA to effectaccess and connections of a block cluster. Again, bi-directionalpassgate switches are programmed by the user to effect the desiredconnections. By implementing level 2 MLA routing network, programmableinterconnections between even larger numbers of logical blocks isachieved.

[0065] Additional levels of MLA routing networks can be implemented toprovide programmable interconnections for ever increasing numbers andgroups of logical blocks, block clusters, block sectors, etc. Basically,the present invention takes a three dimensional approach forimplementing routing. Signals are routed amongst the intraconnections ofa logical block. These signals can then be accessed through blockconnectors and routed according to the programmed connections of theblock connectors. If needed, signals are “elevated” to the level 1 MLA,routed through the level 1 MLA routing network, “de-elevated” to theappropriate block connectors, and then passed to the destination logicalblock.

[0066] If level 2 MLA routing network is required, some of the signalsare elevated a second time from a level 1 MLA routing network line ordirectly to the level 2 MLA routing network, routed to a different setof level 2 MLA routing network line, and “de-elevated” from the level 2MLA routing network line to a Level 1 MLA routing network line.Thereupon, the signals are “de-elevated” a second time to pass thesignal from the level 1 MLA to the appropriate block connectors of thedestination logical block. Alternatively, the “elevation” can beachieved directly without passing through the level 1 MLA routingnetwork. This same approach is performed for level 3, 4, 5, etc. MLAs onan as needed basis, depending on the size and density of the FPGA.Partial level n MLA can be implemented using the above discussed methodto implement a FPGA with a given cell array count.

[0067]FIG. 4A shows an example of a logical cluster and the associatedvertical block connectors within the logical block. In the currentlypreferred embodiment, each cell in a logical cluster is accessible fromthe input by two vertical block connectors and each output of the cellin a logical cluster is accessible to two of the vertical blockconnectors. For example, input A of cell 301 is accessible to thevertical block connectors 451 (BC-V11) and 453 (BC-V21) through switches467, 462 respectively, input B of cell 301 is accessible to the verticalblock connectors 452 (BC-V12) and 454 (BC-V22) through switches 466, 468respectively, output X of cell 301 is accessible to the vertical blockconnectors 455 (BC-V31) and 458 (BC-V42) through switches 460, 459respectively. Input A of cell 302 is accessible to the vertical blockconnectors 453 (BC-V21) and 455 (BC-V31) through switches 463, 464respectively, input B of cell 302 is accessible to the vertical blockconnectors 454 (BC-V22) and 456 (BC-V32) through switches 469, 470respectively, output X of cell 302 is accessible to the vertical blockconnectors 452 (BC-V12) and 457 (BC-V41) through switches 461, 465respectively. Input A of cell 303 is accessible to the vertical blockconnectors 451 (BC-V11) and 453 (BC-V21) through switches 485, 476respectively, input B of cell 303 is accessible to the vertical blockconnectors 452 (BC-V12) and 454 (BC-V22) through switches 480, 476respectively, output X of cell 303 is accessible to the vertical blockconnectors 455 (BC-V31) and 458 (BC-V42) through switches 472, 471respectively. The input A of cell 304 is accessible to the verticalblock connectors 453 (BC-V21) and 455 (BC-V31) through switches 477, 478respectively, input B of cell 304 is accessible to the vertical blockconnectors 454 (BC-V22) and 456 (BC-V32) through switches 482, 484respectively, output X of cell 304 is accessible to the vertical blockconnectors 452 (BC-V12) and 457 (BC-V41) through switches 475,474respectively. D flip-flop cell 305 input is accessible to the verticalblock connectors 454 (BC-V22) and 455 (BC-V31) through switches 473,479respectively, output X of cell 305 is accessible to the vertical blockconnectors 452 (BC-V12) and 457 (BC-V41) through switches 483, 486respectively.

[0068] In similar fashion, FIG. 4B shows the possible connectionscorresponding to horizontal block connectors and the logical clustershown in FIG. 4A. Input A of cell 301 is accessible to the horizontalblock connectors 402 (BC-H12) and 404 (BC-H22) through switches 409, 413respectively, input B of cell 301 is accessible to the horizontal blockconnectors 401 (BC-H11) and 403 (BC-H21) through switches 415, 416respectively, output X of cell 301 is accessible to the horizontal blockconnectors 405 (BC-H31) and 408 (BC-H42) through switches 421, 428respectively. Input A of cell 302 is accessible to the horizontal blockconnectors 402 (BC-H12) and 404 (BC-H22) through switches 411, 414respectively, input B of cell 302 is accessible to the horizontal blockconnectors 401 (BC-H11) and 403 (BC-H21) through switches 433, 417respectively, output X of cell 302 is accessible to the horizontal blockconnectors 405 (BC-H31) and 408 (BC-H42) through switches 418,424respectively. Input A of cell 303 is accessible to the horizontal blockconnectors 404 (BC-H22) and 406 (BC-H32) through switches 419, 426respectively, input B of cell 303 is accessible to the horizontal blockconnectors 403 (BC-H21) and 405 (BC-H31) through switches 420, 425respectively, output X of cell 303 is accessible to the horizontal blockconnectors 402 (BC-H12) and 407 (BC-H41) through switches 410 427respectively. The input A of cell 304 is accessible to the horizontalblock connectors 404 (BC-H22) and 406 (BC-H32) through switches 422,430respectively, input B of cell 304 is accessible to the horizontal blockconnectors 403 (BC-H21) and 405 (BC-H31) through switches 423,429respectively, output X of cell 304 is accessible to the horizontal blockconnectors 402 (BC-H12) and 407 (BC-H41) through switches 412,434respectively. D flip-flop cell 305 input is accessible to the horizontalblock connectors 403 (BC-H21) and 406 (BC-H32) through switches 436, 431respectively, output X of cell 305 is accessible to the horizontal blockconnectors 401 (BC-H11) and 408 (BC-H42) through switches 432, 435respectively.

[0069]FIGS. 4A and 4B illustrate the vertical and horizontal blockconnectors accessing method to the upper left (NW) logical clusterinside a logical block in the currently preferred embodiment. The lowerleft (SW) cluster has the identical accessing method to the verticalblock connectors as those of the NW cluster. The upper right (NE)cluster has similar accessing method to those of the NW cluster withrespect to the vertical block connectors except the sequence of verticalblock connector access is shifted. The vertical block connectors 451-458can be viewed as chained together as a cylinder (451, 452, . . . , 458).Any shift, say by 4, forms a new sequence: (455, 456, 457, 458, 451,452, 453, 454). Instead of starting with vertical block connectors 451and 453 accessing by cell 301 in the NW cluster as illustrated in FIGS.4A, the cell 301 in the NE cluster is accessible to VBCs 455 and 457.The numbering is “shifted” by four. The access labeling of the lowerright (SE) cluster to the VBCs is identical to those of NE cluster.

[0070] Similarly, the horizontal block connectors access to the NWduster is identical to those of the NE cluster and the SW cluster isidentical to the SE cluster while the horizontal block connectors accessto the SW cluster is shifted by four compared with those of NW duster.

[0071] In the currently preferred embodiment, sixteen block connectorsare used per logical block (i.e. four clusters, or a 4×4 cell array).Adding a level 1 MLA routing network allows for the connectability for ablock cluster (an 8×8 cell array). Adding level 2 MLA routing networkincreases the connectability to a block sector (16×16 cell array).Additional levels of MLA routing network increases the number of blocksectors by factors of four while the length (or reach) of each line inthe MLA routing network increases by factors of two. The number ofrouting lines in the level 2 MLA is increased by a factor of two; sincethe number of block sectors increased by a factor of four, on a per unitarea basis, the number of routing lines in the next level of hierarchyactually decreases by a factor of two.

[0072]FIG. 5A shows a logical block with associated sixteen blockconnectors and level 1 MLA routing lines associated with the logicalblock. The sixteen block connectors 501-516 are depicted by heavy lineswhereas the sixteen level 1 MLA routing network lines 517-532 aredepicted by lighter lines. Note that the length or span of the blockconnectors terminates within the logical block while the length of thelevel 1 MLA routing network lines extends to neighboring logical blocks(twice the length of the block connectors).

[0073] Both block connectors and level 1 MLA routing network lines aresubdivided into horizontal and vertical groups: vertical blockconnectors 501-508, horizontal block connectors 509-516, vertical level1 MLA routing network lines 517-524, and horizontal level 1 MLA routingnetwork lines 525-532.

[0074] In the currently preferred embodiment, there are twenty fourlevel 1 MLA turn points for the sixteen level 1 MLA routing networklines within the logical block. In FIG. 5A, the twenty four turn pointsare depicted as clear dots 541-564. A MLA turn point is a programmablebi-directional passgate for providing connectability between ahorizontal MLA routing network line and a vertical MLA routing networkline. For example, enabling level 1 MLA turn point 541 causes thehorizontal level 1 MLA routing network line 526 and vertical level 1 MLArouting network line 520 to become connected together. FIG. 5B showslevel 1 MLA turn point 541. Switch 583 controls whether level 1 MLArouting network line 526 is to be connected to level 1 MLA routingnetwork line 520. If switch is enabled, then level 1 MLA routing networkline 526 is connected to level 1 MLA routing network line 520.Otherwise, line 526 is not connected to line 520. Switch 583 isprogrammable by the user. The turn points are placed as pair-wise groupswith the objective of providing switching access connecting two or moreblock connectors first through the block connector to level 1 MLAexchange networks and then connecting selected level 1 MLA routing linesby enabling the switches. The level 1 MLA lines are used to connectthose block connectors that reside in separate logical blocks within thesame block cluster.

[0075] Referring back to FIG. 5A, there are eight block connector tolevel 1 MLA exchange networks 533-540 for each logical block. Theseexchange networks operate to connect certain block connectors to level 1MLA lines as programmed by the user. FIG. 5C shows the exchange network537 in greater detail. The block connector to level 1 MLA routingexchange network has eight drivers 575-582. These eight drivers 575-582are used to provide bi-directional drive for the block connectors 501,502 and level 1 MLA lines 517, 518. For example, enabling switch 565causes the signal on block connector 501 to be driven by driver 575 fromthe level 1 MLA line 517. Enabling switch 566 causes the signal on level1 MLA line 517 to be driven by driver 576 from the block connector 501.Enabling switch 567 causes the signal on block connector 501 to bedriven by driver 577 from the level 1 MLA line 518. Enabling switch 568causes the signal on level 1 MLA line 518 to be driven by driver 578from the block connector 501.

[0076] Similarly, enabling switch 569 causes the signal on blockconnector 502 to be driven by driver 579 from the level 1 MLA line 517.Enabling switch 570 causes the signal on level 1 MLA line 517 to bedriven by driver 580 from the block connector 502. Enabling switch 571causes the signal on block connector 502 to be driven by driver 581 fromthe level 1 MLA line 518. Enabling switch 572 causes the signal on level1 MLA line 518 to be driven by driver 582 from the block connector 502.Switch 573 is used to control whether a signal should pass form oneblock connector 501 to the adjacent block connector 584 belonging to theadjacent logical block.

[0077] Likewise, switch 574 is used to control whether a signal shouldpass form one block connector 502 to the adjacent block connector 585belonging to the adjacent logical block.

[0078]FIG. 6 shows the routing network for a block cluster. The blockcluster is basically comprised of four logical blocks which can beinterconnected by the level 1 MLA exchange networks 533-540. It can beseen that there are thirty-two level 1 MLA routing network lines.

[0079]FIG. 7A shows the block diagram for a block sector. The blocksector is comprised of four block clusters 701-704. As discussed above,the block clusters are interconnected by block connectors and level 1MLA routing network lines. In addition, the block sector is alsocomprised of sixty-four level 2 MLA routing network lines and sixty-fourlevel 2 to level 1 exchange networks to provide connectability betweenlevel 1 MLA routing network and level 2 MLA routing network. The level 1to level 2 MLA routing exchange networks are depicted by rectangles inFIG. 7A. Furthermore, there are forty-eight level 2 MLA turn pointsassociated with each of the four logical blocks within the block sector.Consequently, there are one hundred and ninetytwo level 2 MLA turnpoints for the block sector.

[0080]FIG. 7B shows a sample level 1 to level 2 MLA routing exchangenetwork 705. It can be seen that switch 710 is used to control whether asignal should pass between level 1 MLA line 709 and level 2 MLA line708. Switch 711 is used to control whether a signal should pass betweenlevel 1 MLA line 709 and level 2 MLA line 707. Switch 712 is used tocontrol whether a signal should pass between level 1 MLA line 706 andlevel 2 MLA line 708. Switch 713 is used to control whether a signalshould pass between level 1 MLA line 706 and level 2 MLA line 707.Switch 714 is used to control whether a signal should pass form onelevel 1 MLA line 709 to the adjacent level 1 MLA line 716 belonging tothe adjacent block cluster. Likewise, switch 715 is used to controlwhether a signal should pass form one level 1 MLA line 706 to theadjacent level 1 MLA line 715 belonging to the adjacent block cluster.

[0081]FIG. 8A shows a sector cluster. The sector cluster is comprised offour block sectors 801-804 with their associated block connectors, level1, and level 2 MLA routing network lines and exchange networks. Inaddition, there are one hundred and twenty-eight level 3 MLA routingnetwork lines, providing connectability between the level 2 MLA linesthat belong to different block sectors 801-804 within the same sectorcluster 800. There are ninety-six level 3 MLA turn points associatedwith the level 3 MLA lines for each of the block sector 801-804 (i.e.three hundred and eighty-four total level 3 MLA turn points for thesector cluster). Furthermore, there are thirty-two level 2 to level 3MLA routing exchange networks associated with each of the four blocksector 801-804. Hence, there are total of one hundred and twenty-eightlevel 3 MLA routing exchange network for providing programmableconnectability between the various level 2 and level 3 MLA lines.

[0082]FIG. 8B shows an example of a level 2 to level 3 MLA routingexchange network 805. It can be seen that enabling switch 810 causes asignal on the level 2 MLA line 808 to be connected to the level 3 MLAline 806. Disabling switch 810 disconnects the level 2 MLA line 808 fromthe level 3 MLA line 806. Enabling switch 811 causes a signal on thelevel 2 MLA line 808 to be connected to the level 3 MLA line 807.Disabling switch 811 disconnects the level 2 MLA line 808 from the level3 MLA line 807. Likewise, enabling switch 812 causes a signal on thelevel 2 MLA line 809 to be connected to the level 3 MLA line 806.Disabling switch 812 disconnects the level 2 MLA line 809 from the level3 MLA line 806. Enabling switch 813 causes a signal on the level 2 MLAline 809 to be connected to the level 3 MLA line 807. Disabling switch813 disconnects the level 2 MLA line 809 from the level 3 MLA line 807.

[0083] In the present invention, larger and more powerful FPGAs can beachieved by adding additional logic sector clusters which are connectedby additional levels of MLA routing networks with the corresponding MLAturn points and exchange networks.

[0084] In one embodiment of the present invention, each of the fiveI-Matrix lines (331-335, FIG. 3A) can be extended to provideconnectability between two adjacent I-Matrix lines belonging to twodifferent clusters. The passgate switches 336-340, 341-345, 346-350, and351-355 in FIG. 3B are examples of four different sets of I-Matrix lineextension switches. This provides further flexibility by providing thecapability of routing a signal between two adjacent clusters withouthaving to be routed through the use of block connectors.

[0085] Similarly, block connectors can be extended to provideconnectability between two adjacent block connectors belonging to twodifferent logical blocks. Switch 573 of FIG. 5C illustrates such blockconnector extension connecting block connector 501 to block connector584 through switch 573. This provides further flexibility by providingthe capability of routing a signal between two adjacent logical blockswithout having to be routed through the level 1 MLA lines and associatedMLA exchange networks. This concept can be similarly applied to thelevel 1 MLA lines as well. Switch 714 of FIG. 7B shows an example wherelevel 1 MLA line 709 is extended to connect to level 1 MLA line 716 byenabling switch 714. This provides further flexibility by providing thecapability of routing a signal between two adjacent block clusterswithout having to be routed through the level 2 MLA lines and associatedMLA exchange networks.

[0086]FIG. 9 shows one embodiment of a hierarchical multiple levelrouting network for providing routability between the logical blocks andthe MLA levels. Eight logical blocks 901-908 are shown. Associated witheach of the logical blocks 901-908 are a plurality of block connectors.In the currently preferred embodiment, there are eight horizontal andeight vertical block connectors associated with each of the logicalblocks 901-908. For clarity and ease of comprehension, the blockconnectors corresponding to an individual logical block is representedby a single line (e.g., block connectors 909-916 respectively correspondto logical blocks 901-908) and only the horizontal block connectors areshown.

[0087] In turn, each of the block connectors 909-916 are respectivelycoupled to programmable bi-directional drivers 917-924. Consequently,block connectors 909-916 can be programmed to be coupledbi-directionally to the MLA-1 lines 925-928. For example, exchangenetwork 917 can be programmed to couple one of the block connectors 909of logical block 901 to the MLA-1 line 925. Additional programmablebi-directional drivers 929-932 are used to provide interconnectionsbetween the MLA-1 lines 925-928 and the next MLA level, MLA-2 lines933-934. Programmable bi-directional drivers 935-936 selectively provideinterconnections between the MLA-2 lines 933-934 and the MLA-3 line 937.This hierarchical interconnection scheme can be repeated for additionalmultiple MLA levels.

[0088]FIG. 10 shows another embodiment of a hierarchical multiple levelrouting network for providing routability between the logical blocks andthe MLA levels. This embodiment is similar to the routing network shownin FIG. 9, except that the block connectors can be directly connected toany of the MLA levels and bypassing any intervening MLA level. Eightlogical blocks 1001-1008 are shown. Associated with each logical blockare a plurality of block connectors 1009-1016. Programmablebi-directional drivers 1017-1024 are used to selectively couple theblock connectors 1009-1016 to the block connector tabs 1025-1032. Theblock connector tabs 1025-1032 are used as junction points from whichconnections can be made to multiple MLA layers. Programmablebi-directional driver sets (1033-1035), (1036-1038), (1039-1041),(1042-1044), (1045-1047), (1048-1050), (1051-1053), (1054-1056),correspond to block connector tabs 1025-1032, respectively. Each ofthese driver sets enables their respective logical block to be connectedto either the MLA-1 line 1061, MLA-2 line 1062, or MLA-3 line 1063without requiring it to pass through any intervening MLA lines. Forexample, logical block 1001 can be connected to the MLA-1 line 1061 byselectively activating drivers 1017 and 1033. Logical block 1001 canalso be connected to the MLA-2 line 1062 by selectively activatingdrivers 1017 and 1034. Note that in this embodiment, logical block 1001can be connected to the MLA-2 line 1062 without having to first beconnected to the MLA-1 line 1061. Furthermore, logical block 1001 can beconnected to the MLA-3 line 1063 by selectively activating drivers 1017and 1035. Note that in this embodiment, logical block 1001 need not beconnected to either the MLA-1 nor the MLA-2 layers in order for it to beconnected to the MLA-3 layer. By directly connecting the logical blockto the desired MLA layer, the speed of the overall routing network isimproved. Furthermore, speed and routing flexibility can be enhanced bydirectly connecting two or more adjacent logical blocks. Thereby,adjacent logical blocks can communicate without having to be routed overany of the MLA layers. For example, logical blocks 1001 and 1002 can beconnected together via the programmable bi-directional driver 1057;logical blocks 1003 and 1004 can be connected via driver 1058; andlogical blocks 1005-1007 can be connected via drivers 1059-1060. Thishierarchical routing scheme can readily be any number of logical blocksand MLA layers. In addition, a passgate 1064 can be included to coupleblock connector 1010 corresponding to logic block 1002 to blockconnector 1011 corresponding to logic block 1003.

[0089]FIG. 11 shows a block diagram of one embodiment of thehierarchical routing network wherein two groups of block connectorsaccess the same MLA lines. A first group of logical blocks 1101-1104 anda second group of logical blocks 1105-1108 are shown. The first group oflogical blocks 1101-1104 can be selectively connected to the MLA-1 layer1109 and 1121, MLA-2 layer 1110, MLA-3 layer 1111, and MLA Tab 1112 viablock connector tabs 1113-1116. Similarly, the second group of logicalblocks 1105-1108 can be selectively connected to the MLA-1 layer 1109and 1121, MLA-2 layer 1110, MLA-3 layer 1111, and MLA Tab 1112 via theirrespective block connector tabs 1117-1120.

[0090]FIG. 12 shows a block diagram of part of the multiple levelrouting network which encompasses Block Connectors to the MLA-3 Levelwith MLA Tabs for higher levels of routing network (the I-Matrix is notshown). FIG. 12 shows the interconnections of one set of BlockConnectors and its corresponding higher levels of MLAs in the horizontaldirection. There is also a corresponding perpendicular (e.g., vertical)group of routing network interconnecting the Block Connectors and theassociated MLAs. This perpendicular group is not shown in FIG. 12 inorder to avoid obscuring the present invention. Note that there is acorresponding copy of the routing network for each and every BlockConnector and associated MLAs of the FPGA.

[0091] Shown in FIG. 12 are thirty-two blocks 1201-1232. Each block isassociated with a distinct and adjacent block along with two BC tabs(e.g., one horizontal and one vertical). Each of the Block Connectors1201-1232 are coupled to two selectable BC Tabs via a programmableswitch. For example, block connector 1201 is coupled to selectable BCTab 1233 through programmable switch 1234. The second group of BC Tabs,which is perpendicular (e.g., vertical) to the first BC Tab group is notshown. A similar BC Tab interconnection scheme exists for blockconnectors 1217-1232 (both horizontally and vertically). For each BCTab, there are bi-directional programmable drivers connectable to theMLA-1 routing lines. For example, BC Tab 1233 is selectively connectableto the MLA-1 routing line 1235 via drivers 1236. These drivers caneither be parallel to or perpendicular to the corresponding BC Tabs. Inthe currently preferred embodiment, the number of MLA-1 lines is halfthe number of Block Connectors, since for each Block Connector, there isa corresponding MLA-1 line plus another MLA-1 line which isperpendicular to the first MLA-1 line. Each MLA-1 line is connectablethrough programmable means to the corresponding Block Connector, MLA-2,and MLA-3 lines through their corresponding BC Tab. Note that the MLA-1routing network together with I-Matrix lines and Block Connectors formthe routing resources in a 2×2 Block area. This format enhances morecomplex logic function formation accessing and interconnecting thecells. Furthermore, the MLA-1 routing network, in addition to bothI-Matrix lines and Block Connectors, become additional bi-directionallyprogrammable access lines that can serve as access ports for theimplementation of even more complex logic functions through connectionsby other MLA lines or Block Connectors from outside of the 2×2 Blockarea. By using programmable switches, the I-Matrix lines and blockconnectors can be selectively accessed which are not necessarilyadjacent or congruent to the 2×2 Block areas. Hence, the total number ofrouting segments including I-Matrix lines, Block connectors, and MLA-1lines grow geometrically when the growth is from a Block to 2×2 Blocks.

[0092] For each BC Tab, there is bi-directionally programmable driversconnectable to the MLA-2 routing lines. For example, block connector tab1233 is connectable to the MLA-2 line 1237 via drivers 1238. The MLA-2can either be parallel to or perpendicular to the corresponding BC Tabs.In the currently preferred embodiment, the number of MLA-2 lines is halfthe number of MLA-1 lines. Each MLA-2 line is connectable throughprogrammable means to the corresponding Block Connector, MLA-1, andMLA-3 lines through the corresponding BC Tab. The MLA-2 routing networktogether with I-Matrix lines, Block Connectors and MLA-1 routing networkform the routing resources in a 4×4 Block area for more complex logicfunction formation accessing and for interconnecting the cells. In thiscase, the MLA-2 routing network, in conjunction with the I-Matrix lines,Block Connectors and MLA-1 lines, become additional bi-directionallyprogrammable access lines that can serve as access ports for theimplementation of even more complex logic functions through connectionswith other MLA lines or Block connectors from outside of the 4×4 Blockarea. By means of programmable switches, the access need not necessarilybe adjacent or congruent to the 4×4 Block area. The total number ofrouting segments including I-Matrix lines, Block Connectors, MLA-1lines, and MLA-2 lines in a 4×4 Block unit grows proportional to theincrease in logic cells. The increase in the total number is geometricalwhen the growth is from a Block to 4×4 Blocks. Similarly, for each BCTab, there is bi-directionally programmable drivers connectable to MLA-3routing lines. For example, BC Tab 1233 is connectable to the MLA-3 line1239 via drivers 1240. The MLA-3 routing line can either be parallel toor perpendicular (e.g., horizontal or vertical) to the corresponding BCTabs. In the currently preferred embodiment, the number of MLA-3 linesis half the number of MLA-2 lines. Each MLA-3 line is connectablethrough programmable means to the corresponding Block Connector, MLA-1,and MLA-2 lines through the corresponding BC Tab. The MLA-3 routingnetwork together with I-Matrix lines, Block Connectors, MLA-1 routingnetwork and MLA-2 routing network form the routing resources in a 8×8Block area for more complex logic function formation accessing andinterconnecting the cells. The MLA-3 routing network, in addition toboth I-Matrix lines, Block Connectors, MLA-1 lines and MLA-2 lines,become additional bi-directionally programmable access lines that canserve as access ports for the implementation of even more complex logicfunctions through connections by other MLA lines or Block Connectorsthat are outside of the 8×8 Block area and are not necessarily adjacentor congruent to the 8×8 Block area through programmable means. Hence,the total number of routing segment including I-Matrix lines, BlockConnectors, MLA-1 lines, MLA-2 lines and MLA-3 lines in an 8×8 Blockunit grows proportional to the increase in logic cells. This increase isgeometrical when the growth is from a Block to 8×8 Blocks. In addition,for each BC Tab, there is bi-directionally programmable driversconnectable to MLA Tabs. For example, BC Tab 1233 is connectable to theMLA Tab 1241 via drivers 1242. The MLA Tabs can either be parallel to orperpendicular to the corresponding BC Tabs. Each bi-directionallyprogrammable driver (e.g., driver's 1236, 1238, 1240, 1242, etc.) can beeither passgate controlled through programmable means; bi-directionaldrivers with passgates controlled through programmable means; atri-state controlled through programmable means in one direction andpassgate or driver with a passgate controlled through programmablemeans; or two tri-states in opposite directions controlled throughprogrammable means. The choice is a function of speed and densityrequirements.

[0093] In one embodiment, each Block Connector and BC Tab haveextensions to the adjacent Blocks. For example, block 1201 isconnectable to block 1202 via programmable switch 1243. BC Tab 1244 isconnectable to BC Tab 1245 via programmable switch 1246. It should benoted that additional extensions for MLA lines can be implemented inorder to extend the routing range without having to use higher level MLAlines. Multiple variations to the routing network shown in FIG. 12 arepossible. For example, to increase routing resources and henceroutability, the MLA-1 routing network can be replaced by making twocopies of the MLA-2 routing network. On the other hand, if the objectiveis to minimize the routing area, one embodiment minimizes the amount ofprogramming bits by replacing the MLA-1 routing network with a copy ofthe MLA-2 routing network. These kinds of variations can be applied to amixture of other levels. Another embodiment is to off-set one or more ofthe MLA lines. For example, in FIG. 12, the 1247 is accessible by BCTabs 1245, 1248, 1249, and 1250. The MLA-1 line 1247 can be shifted byone block to become accessible by BC Tabs 1248, 1251, 1250, and 1252instead. All other MLA-1 lines can be thusly shifted. This can also beapplied to other MLA level(s).

[0094]FIG. 13 shows an MLA-1 turn network. Four logical blocks 1301-1304are shown. These four logical blocks are connected to each of the MLA-1lines of sets 1305-1308. Each of the MLA-1 lines is connectable througha programmable means (e.g., turn points 1309) to all the perpendicularMLA-1 lines, except the corresponding perpendicular MLA-1 line. Forexample, the horizontal MLA-1 line 1310 is connectable to the verticalMLA-1 line 1311 via turn point 1312. The purpose for the MLA-1 lines isto connect a set of Block Connectors together that is within the MLA-1routing network range. In the case of connecting corresponding BlockConnectors within a four-Blocks area, as shown in FIG. 13, theconnection(s) can be made through either the Block Connector extensionor through a BC Tab to one of the corresponding MLA-1 line, withouthaving to resort to using two perpendicular MLA-2 lines through turnpoints. In one embodiment, the number of turn points is reduced. Thisrestricts the turn flexibility but also reduces both the loading on theMLA-1 lines and the area required to lay out the design. However,routing flexibility and routability may be affected.

[0095]FIG. 14 shows an MLA-2 turn network. As can be seen, each MLA-2line is connectable through programmable means to every MLA-2 lineswhich are perpendicular to the MLA-2 line. For example, the verticalMLA-2 line 1401 is connectable to the horizontal MLA-2 line 1402 throughturn point 1403. In other embodiments, the turn flexibility can be mademore restrictive by reducing the number of turn points. This will reduceboth the loading on the MLA-2 line and the area required to lay out thedesign. However, routing flexibility and routability may be affected.

[0096]FIG. 15 shows an MLA-3 turn network. Each MLA-3 line isconnectable through programmable means to all the perpendicular MLA-3lines. For example, the vertical MLA-3 line 1501 is connectable to thehorizontal MLA-3 line 1502 through turn point 1503. The turn flexibilitycan be made more restrictive by reducing the number of turn points. Thiswill reduce both the loading on the MLA-3 line and the area required tolay out the design. However, routing flexibility and routability may beaffected.

[0097]FIG. 16 shows one embodiment of a routing network for the MLA-4layer and the mechanism whereby the MLA-4 lines are accessed. FIG. 16shows four 8×8 Blocks 1621-1624 (for a total of 16×16 Blocks).Associated with the four 8×8 Blocks 1621-1624 are four horizontal andfour vertical groups of MLA Tabs. In the currently preferred embodiment,the MLA-4 lines and MLA Tabs are 8-bits wide. Since each Block has eightcorresponding Block Connectors, each MLA Tab is shown to be eight lineswide where each of the lines corresponds to one of the 8 BlockConnectors as shown earlier in FIG. 12. In the currently preferredembodiment, there are four vertical and four horizontal MLA-4 lines,each of which is eight lines wide. Thus, the number of MLA-4 lines isone-fourth the number of MLA-3 lines. Each MLA-4 line is connectablethrough programmable means to the corresponding Block Connector, MLA-1,MLA-2 and MLA-3 lines. The desired connectivity is made through thecorresponding MLA Tab and the BC Tab. The MLA-4 routing network togetherwith the I-Matrix lines, Block Connectors, MLA-1 routing network, MLA-2routing network and MLA-3 routing network, form the routing resources ina 16×16 Block area for more complex logic function formation accessingand interconnecting of the cells. In one embodiment, the MLA-4 routingnetwork, in addition to both I-Matrix lines, Block Connectors, MLA-1lines, MLA-2 lines and MLA-3 lines become additional bi-directionallyprogrammable access lines that can serve as access ports for theimplementation of even more complex logic functions through connectionsby other MLA lines of Block Connectors from outside of the 16×16 Blockarea through programmable means. These other MLA lines or blockconnectors need not necessarily be adjacent or congruent to the 16×16Block area. The total number of routing segments including I-Matrixlines, Block connectors, MLA-1 lines, MLA-2 lines, MLA-3 lines and MLA-4lines in a 16×16 Block unit grows proportional to the increase in logiccells. The increase in size is geometrical when the growth is from aBlock to 16×16 Blocks. From each MLA Tab there is a corresponding MLA-4line connectable to the MLA Tab via a switch. For example, MLA Tab 1601is connectable to MLA-4 line 1602 via switch 1603. Similarly, MLA Tab1601 is connectable to MLA-4 line 1604 via switch 1605; MLA-4 line 1606via switch 1607; and MLA-4 line 1608 via switch 1609. Likewise, MLA Tab1610 is connectable to MLA-4 lines 1611-1614 via switches 1615-1618,respectively. Each MLA Tab in any one of the four corners is connectablethrough programmable means to all the corresponding MLA Tabs in all fourcorners through the vertical or the horizontal MLA-4 lines.

[0098]FIG. 17 shows three different switch embodiments 1701-1703. Ingeneral, the switch is a bi-directionally programmable driver networkwhich can be a simple bi-directional passgate, or any of thebi-directional driver configurations 1701-1703.

[0099]FIG. 18 shows one embodiment of a routing network for the MLA-5layer and the mechanism whereby MLA-5 lines are accessed. Sixteen 8×8Blocks are shown. Associated with each of the 8×8 Blocks are fourhorizontal and four vertical MLA Tabs, which are the same as the MLATabs shown in FIG. 16. When the 16×16 Blocks (as shown in FIG. 16) aregrouped as a unit, the next higher level, which consists of 32×32Blocks, is formed. Associated with each of the four 16×16 corner unitsare four horizontal and four vertical MLA-5 lines, each 8-bit wide.These lines are shared by the adjacent corner units, as shown in FIG.18. Thus, the number of MLA-5 lines is half the number of MLA-4 lines.Each MLA-5 line is connectable through programmable means to thecorresponding Block Connector, MLA-1, MLA-2, MLA-3 and MLA-4 linesthrough the corresponding MLA Tab and the BC Tab. The MLA-5 routingnetwork together with I-Matrix lines, Block Connectors, MLA-1 routingnetwork, MLA-2 routing network, MLA-3 routing network and MLA-4 routingnetwork form the routing resources in a 32×32 Block area for morecomplex logic function formation accessing and interconnecting thecells. Furthermore, the MLA-5 routing network, in addition to bothI-Matrix lines, Block Connectors, MLA-1 lines, MLA-2 lines, MLA-3 linesand MLA-4 lines can be used as additional bi-directionally programmableaccess lines that can serve as access ports for the implementation ofeven more complex logic functions through connections by other MLA linesor Block Connectors from outside of the 32×32 Block area (which need notnecessarily be adjacent or congruent to the 32×32 Block area) throughprogrammable means. The total number of routing segments includingI-Matrix lines, Block Connectors, MLA-1 lines, MLA-2 lines, MLA-3 lines,MLA-4 lines and MLA-S lines in a 32×32 Block unit grows proportional tothe increase in logic cells. This increase is geometrical when thegrowth is from a Block to 32×32 Blocks.

[0100] From each MLA Tab there is a corresponding MLA-5 line connectableto the MLA Tab via a switch. The switch is a bi-directionallyprogrammable driver network which can be a simple bi-directionalpassgate, or any of the bi-directional driver configurations as shown inFIG. 17. In addition, turn points are incorporated where the verticalMLA-5 lines intersect the horizontal MLA-5 lines through programmablemeans. Each MLA Tab in any one of the four corners is connectablethrough programmable means to all the corresponding MLA Tabs in all fourcorners. This is implemented by a combination of programmableconnections to the vertical and the horizontal MLA-5 lines plus use ofthe turn points.

[0101] Higher levels of MLA networks can be developed by programmableaccess through the MLA Tabs or by introducing another new intermediateMLA Tabs. In such instances, the number of MLA lines is a fraction ofthe next lower level MLAs. The total number of routing segmentsincluding I-Matrix lines, Block Connectors, MLA-1 lines, MLA-2 lines,MLA-3 lines, MLA-4 lines, MLA-5 lines and higher levels of MLA lines,and the corresponding number of n×n Block unit grows proportional to theincrease in logic cells. This increase is geometrical when the growth isfrom a Block. to the n×n Blocks.

[0102] Thus, an architecture with an intraconnect and interconnectscheme for programmable logic circuits is disclosed.

What is claimed is:
 1. A programmable logic circuit comprising: aplurality of logic blocks having a plurality of programmableinterconnected cells for performing logic functions on logic signals; afirst set of programmable switches coupled to said plurality of cells ofsaid plurality of logic blocks; a first set of routing lines coupled tosaid first set of programmable switches to form a first set ofbi-directionally programmable access lines to said plurality of logicblocks, wherein said first set of bi-directionally programmable accesslines function as input/output pins for said plurality of logic blocksthrough programmable means; a second set of programmable switchescoupled to said first set of bi-directionally programmable access lines;a second set of routing lines coupled to said second set of programmableswitches.
 2. The programmable logic circuit of claim 1 furthercomprising: a third set of programmable switches for selectivelycoupling a plurality of lines of said second set of routing lines,wherein said second set of routing lines and said third set ofprogrammable switches comprise a first level of interconnections; athird set of routing lines connectable to said second set ofprogrammable switches.
 3. The programmable logic circuit of claim 2further comprising: a fourth set of programmable switches forselectively coupling a plurality of lines of said third set of routinglines, wherein said third set of routing lines and said fourth set ofprogrammable switches comprise a second level of interconnections; afifth set of programmable switches connectable between said third set ofrouting lines and said second set of routing lines for selectivelycoupling said plurality of logic blocks to said second level ofinterconnections via said first level of interconnections.
 4. Theprogrammable logic circuit of claim 1 further comprising: a sixth set ofprogrammable switches for selectively coupling a line of said first setof bi-directionally programmable access lines of a first logic block toa line of said first set of bi-directionally programmable access linesof a second logic block, wherein first said logic block is adjacent tosaid second logic block.
 5. The programmable logic circuit of claim 4wherein the number of lines of said first set of routing lines for eachlogic block of said plurality of logic blocks is approximately half thenumber of said plurality of cells of said logic block.
 6. Theprogrammable logic circuit of claim 2, wherein the span of each of thesaid second set of routing lines is twice the span of each of said firstset of routing lines.
 7. The programmable logic circuit of claim 2,wherein the number of said second set of routing lines is half thenumber of said first set of routing lines.
 8. The programmable logiccircuit of claim 3, wherein the span of each of said third set ofrouting lines is twice the span of each of said second set of routinglines.
 9. The programmable logic circuit of claim 3, wherein the numberof said third set of routing lines is half the number of the said secondset of routing lines.
 10. The programmable logic circuit of claim 1further comprising: a fourth set of routing lines connectable to saidsecond set of programmable switches; a seventh set of programmableswitches for selectively coupling a plurality of lines of said fourthset of routing lines, wherein said fourth set of routing lines and saidseventh set of programmable switches comprise a third level ofinterconnections; an eighth set of programmable switches connectablebetween said fourth set of routing lines and said third set of routinglines for selectively coupling said plurality of logic blocks to saidthird level of interconnections via said second level ofinterconnections or said first level of interconnections.
 11. Theprogrammable logic circuit of claim 10, wherein the span of each of saidfourth set of routing lines is twice the span of each of said third setof routing lines and the number of said fourth set of routing lines ishalf the number of said third set of routing lines.
 12. The programmablelogic circuit of claim 10, wherein said fourth set of routing lines andsaid seventh set of programmable switches comprise a third level ofinterconnections.
 13. The programmable logic circuit of claim 1 furthercomprising: a fifth set of routing lines, connectable to said second setof programmable switches for forming a fourth level of interconnections.14. The programmable logic circuit of claim 13, wherein the span of eachof said fifth set of routing lines is twice the span of each of saidthird set of routing lines.
 15. The programmable logic circuit of claim13, wherein the number of said fifth set of routing lines is half of thenumber of said third set of routing lines.
 16. The programmable logiccircuit of claim 1 further comprising: a sixth set of routing linescomprising a fifth level of interconnections; a ninth set ofprogrammable switches connectable between said sixth set of routinglines and said fifth set of routing lines capable of conducting signalfrom said first set of bi-directionally programmable access lines forselectively coupling said plurality of logic blocks to said fifth levelof interconnections via said fourth level of interconnections andbypassing said first level of interconnections, said second level ofinterconnections, and said third level of interconnections.
 17. Theprogrammable logic circuit of claim 16, wherein the span of each of saidsixth set of routing lines is twice the span of each of said fourth setof routing lines.
 18. The programmable logic circuit of claim 16,wherein the number of said sixth set of routing lines is one fourth thenumber of said fourth set of routing lines.
 19. The programmable logiccircuit of claim 1 further comprising: a seventh set of routing lines; atenth set of programmable switches coupled for selectively connecting aplurality of lines of said seventh set of routing lines, wherein saidseventh set of routing lines and said tenth set of programmable switchescomprise a sixth level of interconnections; an eleventh set ofprogrammable switches connectable between said seventh set of routinglines and said fifth set of routing lines capable of conducting signalfrom said first set of bi-directionally programmable access lines forselectively coupling said plurality of logic via said fourth level ofinterconnections and bypassing said first level of interconnections,said second level of interconnections, said third level ofinterconnections, and said fifth level of interconnections.
 20. Theprogrammable logic circuit of claim 19, wherein the span of each of saidseventh set of routing lines is twice the span of each of said sixth setof routing lines.
 21. The programmable logic circuit of claim 19,wherein the number of said seventh set of routing lines is half thenumber of said sixth set of routing lines.
 22. The programmable logiccircuit of claim 1, wherein said first level of interconnectionsfunction as a second set of bi-directionally programmable access lines.23. The programmable logic circuit of claim 2, wherein said second levelof interconnections function as third set of bi-directionallyprogrammable access lines.
 24. The programmable logic circuit of claim1, wherein said switches are comprised of bi-directionally programmabledrivers.
 25. The programmable logic circuit of claim 1, wherein saidswitches are comprised of bi-directionally programmable passgates. 26.The programmable logic circuit of claim 1 further comprising a twelfthset of programmable switches for selectively coupling an adjacent set offirst set of bi-directionally programmable access lines of an adjacentset of logic blocks to said same first level of interconnections. 27.The programmable logic circuit of claim 1 further comprising athirteenth set of programmable switches for selectively coupling anadjacent set of first set of bi-directionally programmable access linesof an adjacent set of logic blocks to a same second level ofinterconnections.
 28. The programmable logic circuit of claim 10 furthercomprising a fourteenth set of programmable switches for selectivelycoupling an adjacent set of first set of bi-directionally programmableaccess lines of an adjacent set of logic blocks to said same third levelof interconnections.
 29. The programmable logic circuit of claim 13further comprising a fifteenth set of programmable switches forselectively coupling an adjacent set of first set of bi-directionallyprogrammable access lines of an adjacent set of logic blocks to a samefourth level of interconnections.
 30. The programmable logic circuit ofclaim 16 further comprising a sixteenth set of programmable switches forselectively coupling an adjacent set of said fourth level ofinterconnections to a same fifth level of interconnections.
 31. Theprogrammable logic circuit of claim 19 further comprising a seventeenthset of programmable switches for selectively coupling an adjacent set ofsaid fourth level of interconnections to a same sixth level ofinterconnections.
 32. The programmable logic circuit of claim 10,wherein said third level of interconnections function as fourth set ofbi-directionally programmable access lines.
 33. The programmable logiccircuit of claim 13, wherein said fourth level of interconnectionsfunction as fifth set of bi-directionally programmable access lines. 34.The programmable logic circuit of claim 16, wherein said fifth level ofinterconnections function as sixth set of bi-directionally programmableaccess lines.
 35. The programmable logic circuit of claim 19, whereinsaid sixth level of interconnections function as seventh set ofbi-directionally programmable access lines.
 36. A programmable logiccircuit of claim 1 further comprising: a plurality of logic clusters,each of said logic clusters having a plurality of programmableinterconnected cells for performing logic functions on logic signals; aneighteenth set of programmable switches coupled to said plurality oflogic cells of a said logic cluster, an eighth set of routing linescoupled to said eighteenth set of programmable switches to form a set ofintraconnection matrix routing lines coupled to said logic cluster. 37.The programmable logic circuit of claim 36, wherein said set ofintraconnection matrix routing lines function as short distanceconnections for the said plurality of logic cells of the said logiccluster through programmable means.
 38. The programmable logic circuitof claim 36, the number of lines in each said set of intraconnectionmatrix routing lines is equal to approximately half the number of totalnumber of input pins and output pins of the said plurality of cells insaid logic cluster.
 39. The programmable logic circuit of claim 36, thespan for each line of said set of intraconnection matrix routing linesis equal to half the span of each line of said first set ofbi-directionally programmable access lines.
 40. The programmable logiccircuit of claim 36, said cells of a said logic block are comprised ofsaid plurality of cells of said plurality of logic clusters.
 41. Theprogrammable logic circuit of claim 36 further comprising a nineteenthset of programmable switches for selectively coupling a line of said setof intraconnection matrix of a first logic cluster to a line of the saidset of intraconnection matrix of a second logic cluster, wherein saidfirst logic cluster is adjacent to said second logic cluster.
 42. Aprogrammable logic circuit comprising: a plurality of logic clusters,each of said logic clusters having a plurality of programmablyinterconnected cells for performing logic functions on logic signals; aset of intraconnection matrix routing lines coupling a set of saidplurality of logic clusters; a plurality of logic blocks, each of saidlogic blocks having a plurality of programmably interconnected cells forperforming logic functions on logic signals; a first set ofbi-directionally programmable access lines coupling a first set of saidplurality of logic blocks.
 43. The programmable logic circuit of claim42 further comprising a first level of interconnections coupling atleast two of said first set of bi-directionally programmable accesslines.
 44. The programmable logic circuit of claim 43 further comprisinga first programmable switch coupled to a bi-directionally programmableaccess line of said first set of bi-directionally programmable accesslines of a first logic block for programmably conducting a signalcorresponding to said first logic block to said first level ofinterconnections.
 45. The programmable logic circuit of claim 44 furthercomprising a second level of interconnections coupling at least two ofsaid first level of interconnections.
 46. The programmable logic circuitof claim 45 further comprising a second programmable switch connectableto said bi-directionally programmable access line of said first set ofbi-directionally programmable access lines of said first logic block forprogrammably conducting said signal corresponding to said first logicblock to said second level of interconnections, wherein said first levelof interconnections is capable of being bypassed by said signal.
 47. Theprogrammable logic circuit of claim 46 further comprising: a third levelof interconnections coupling at least two of said second level ofinterconnections.
 48. The programmable logic circuit of claim 47 furthercomprising a third programmable switch connectable to saidbi-directionally programmable access line of said first set ofbi-directionally programmable access lines of said first logic block forprogrammably conducting said signal corresponding to said first logicblock to said third level of interconnections, wherein said first levelof interconnections and said second level of interconnections arecapable of being bypassed by said signal.
 49. The programmable logiccircuit of claim 42 further comprising: a fourth level ofinterconnections; a routing line coupled to said fourth level ofinterconnections; a fourth programmable switch connectable to saidbi-directionally programmable access line of said first set ofbi-directionally programmable access lines of said first logic block forprogrammably conducting said signal corresponding to said first logicblock to said routing line.
 50. The programmable logic circuit of claim42 further comprising a fifth programmable switch connectable to saidintraconnection matrix routing line of said set of intraconnectionmatrix routing lines of said first logic cluster for programmablyconducting said signal corresponding to said intraconnection matrixrouting line of said set of intraconnection matrix routing lines of saidfirst logic cluster to a intraconnection matrix routing line of said setof intraconnection matrix routing lines of a second logic cluster,wherein said first logic cluster is adjacent to said second logiccluster.
 51. The programmable logic circuit of claim 42 furthercomprising a fifth programmable switch connectable to saidbi-directionally programmable access line of said first set ofbi-directionally programmable access lines of said first logic block forprogrammably conducting said signal corresponding to saidbi-directionally programmable access line of said first set ofbi-directionally programmable access lines of said first logic block toa bi-directionally programmable access line of a first set ofbi-directionally programmable access lines of a second logic block,wherein said first level of interconnections are capable of beingbypassed and wherein said first logic block is adjacent to said secondlogic block.
 52. The programmable logic circuit of claim 42 wherein saidswitches are comprised of bi-directionally programmable drivers.
 53. Theprogrammable logic circuit of claim 42 wherein said switches arecomprised of bi-directionally programmable passgates.
 54. Theprogrammable logic circuit of claim 43 further comprising a sixth set ofprogrammable switches for selectively coupling an adjacent set of firstset of bi-directionally programmable access lines of the adjacent set oflogic blocks to said first level of interconnections.
 55. In aprogrammable logic circuit having a plurality of cells for performinglogic functions on logic signals, a method of forming complex logicfunctions for programmably coupling a group of said cells by routingsignals from one of said cells to another of said cells, said methodcomprising the steps of: programmably interconnecting a plurality ofsaid cells to form a first logic cluster, a second logic cluster, and athird logic cluster via a set of intraconnection matrix routing lines;programmably conducting a signal corresponding to a first set ofintraconnection matrix routing lines of a first logic cluster to a firstset of intraconnection matrix routing lines of said second logic clustervia a first set of bi-directionally programmable access lines;programmably interconnecting a plurality of said cells to form a firstlogic block, a second logic block, and a third logic block; programmablyconducting a signal corresponding to a first set of bi-directionallyprogrammable access lines of a first logic block to a first set ofbi-directionally programmable access lines of said second logic blockvia a first level of interconnections.
 56. The method of claim 55,wherein the span of each of the said first set of intraconnection matrixrouting lines is a fraction of the span of each of the said first set ofbi-directionally programmable access lines and the number of lines ofthe said set of intraconnection matrix routing lines is a fraction ofthe number of input and output pins of said cells in said logic cluster.57. The method of claim 55, wherein the span of each of the said firstset of bi-directionally programmable access lines is a fraction of thespan of each of the said first level of interconnections lines and thenumber of lines of the said first level of interconnections lines is afraction of the number of the said first set of bi-directionallyprogrammable access lines over a logic block circuit area.
 58. Themethod of claim 55 further comprising the step of: programmablyconducting said signal to a first set of bi-directionally programmableaccess lines of said third logic block via a second level ofinterconnections by conducting said signal through said first level ofinterconnections.
 59. The method of claim 55 further comprising the stepof: programmably conducting said signal to a first set ofbi-directionally programmable access lines of said third logic block viaa second level of interconnections without conducting said signalthrough said first level of interconnections.
 60. The method of claim58, wherein the span of each of the said first level of interconnectionslines is a fraction of the span of each of said second level ofinterconnections lines and the number of lines of the said second levelof interconnections lines is a fraction of the number of the said firstlevel of interconnections lines over total logic blocks circuit area.61. The method of claim 55 further comprising the step of programmablyconducting said signal to a first set of bi-directionally programmableaccess lines of a fourth logic block via a third level ofinterconnections by conducting said signal through said first level ofinterconnections or said second level of interconnections.
 62. Themethod of claim 55 further comprising the step of programmablyconducting said signal to a first set of bi-directionally programmableaccess lines of a fourth logic block via a third level ofinterconnections without conducting said signal through said first levelof interconnections or said second level of interconnections.
 63. Themethod of claim 62, wherein the span of each of the said second level ofinterconnections lines is a fraction of the span of each of the saidthird level of interconnections lines and the number of lines of thesaid third level of interconnections lines is a fraction of the numberof the said second level of interconnections lines over a logic blockcircuit area.
 64. The method of claim 55 further comprising the step ofprogrammably conducting said signal to a routing line coupled to afourth level of interconnections, wherein the span for each of the lineand the number of lines of the said fourth level of interconnections areproportional to the said third level of interconnections.
 65. The methodof claim 55 further comprising the step of programmably conducting saidsignal directly to said second logic cluster and bypassing said firstset of bi-directionally programmable access lines.
 66. The method ofclaim 55 further comprising the step of programmably conducting saidsignal directly to said second logic block and bypassing said firstlevel of interconnections.
 67. The method of claim 55 further comprisingthe step of programmably conducting said signal to a first set ofbi-directionally programmable access lines of a fifth logic block via afifth level of interconnections via said fourth level ofinterconnections by conducting said signal through said first level ofinterconnections, said second level of interconnections, or said thirdlevel of interconnections.
 68. The method of claim 55 further comprisingthe step of programmably conducting said signal to a first set ofbi-directionally programmable access lines of a fifth logic block via afifth level of interconnections via said fourth level ofinterconnections without conducting said signal through said first levelof interconnections, said second level of interconnections, or saidthird level of interconnections.
 69. The method of claim 68, wherein thespan of each of the said fourth level of interconnections lines is afraction of the span of each of the said fifth level of interconnectionslines and the number of lines of the said fifth level ofinterconnections lines is a fraction of the number of the said fourthlevel of interconnections lines over a logic block circuit area.
 70. Themethod of claim 55 further comprising the step of programmablyconducting said signal to a first set of bi-directionally programmableaccess lines of a sixth logic block via a sixth level ofinterconnections through said fourth level of interconnections byconducting said signal through said first level of interconnections,said second level of interconnections, said third level ofinterconnections, or said fifth level of interconnections.
 71. Themethod of claim 55 further comprising the step of programmablyconducting said signal to a first set of bi-directionally programmableaccess lines of a sixth logic block via a sixth level ofinterconnections through said fourth level of interconnections withoutconducting said signal through said first level of interconnections,said second level of interconnections, said third level ofinterconnections, or said fifth level of interconnections.
 72. Themethod of claim 71, wherein the span of each of the said fifth level ofinterconnections lines is a fraction of the span of each of the saidsixth level of interconnections lines and the number of lines of thesaid sixth level of interconnections lines is a fraction of the numberof the said fifth level of interconnections lines over a logic blockcircuit area.
 73. The method of claim 55 further comprising the step ofselectively coupling an adjacent set of said first set ofbi-directionally programmable access lines of an adjacent set of saidlogic blocks to said first level of interconnections via a set ofprogrammable switches.
 74. The method of claim 55 further comprising thestep of selectively coupling an adjacent set of said first set ofbi-directionally programmable access lines of an adjacent set of saidlogic blocks to said second level of interconnections via a set ofprogrammable switches.
 75. The method of claim 55 further comprising thestep of selectively coupling an adjacent set of said first set ofbi-directionally programmable access lines of an adjacent set of saidlogic blocks to said third level of interconnections via a set ofprogrammable switches.
 76. The method of claim 55 further comprising thestep of selectively coupling an adjacent set of said first set ofbi-directionally programmable access lines of an adjacent set of saidlogic blocks to said fourth level of interconnections via a set ofprogrammable switches.
 77. The method of claim 55 further comprising thestep of selectively coupling an adjacent set of said fourth level ofinterconnections to said fifth level of interconnections via a set ofprogrammable switches.
 78. The method of claim 55 further comprising thestep of selectively coupling an adjacent set of said fourth level ofinterconnections to said sixth level of interconnections via a set ofprogrammable switches.
 79. The method of claim 55, wherein said switchesare comprised of bi-directionally programmable drivers.
 80. The methodof claim 55, wherein said switches are comprised of bi-directionallyprogrammable passgates.
 81. A field programmable gate array comprising:a plurality of cells for performing logic functions on signals input tosaid field programmable gate array; an intraconnection matrix forprogrammably interconnecting a plurality of said cells to form a logiccluster; a plurality of programmable switches connectable between twoadjacent said intraconnection matrices to form logic cluster extensions;a plurality of block connectors together with said logic clusters, saidintraconnection matrices, and said extensions to form a logic block; aplurality of programmable switches connectable between two adjacent saidlogic blocks to form logic block extensions; a first level ofprogrammable interconnections for interconnecting a plurality of logicblocks to form a block cluster; a second level of programmableinterconnections for interconnecting a plurality of block clusters toform a block sector; a first set of programmable switches connecting aplurality of logic blocks to said first level of programmableinterconnections; a second set of programmable switches connecting aplurality of logic blocks to said second level of programmableinterconnections;
 82. The field programmable gate array of claim 81,wherein said logic cluster is comprised of a 2×2 matrix of cells. 83.The field programmable gate array of claim 82, wherein said logic blockis comprised of a 2×2 matrix of logic clusters.
 84. The fieldprogrammable gate array of claim 83, wherein said block cluster iscomprised of a 2×2 matrix of logic blocks.
 85. The field programmablegate array of claim 84, wherein said block sector is comprised of a 2×2matrix of block clusters.
 86. The field programmable gate array of claim81, wherein said first level of interconnections is comprised of a firstset of routing lines and a second set of routing lines perpendicular tosaid first set of routing lines.